Description
Join our ASIC-PD team and work on physical design from RTL to GSDII. Your responsibilities will include:
Design quality check, synthesis, formal check, partitioning, constraint creation and validation, timing budget, and timing closure for both partition and full chip level. Special timing closure, such as io, test, clock etc. Synthesis, Netlist quality check, Formal Verification. Implement chip partition and floorplan. Function eco creation. Develop and enhance entire timing closure flow from frontend (pre-layout) to backend (post-layout). Flow automation development, Methodology in any of above areas.
We're looking for candidates with a Master's degree in EE, CS or Microelectronics, and at least 1 year of experience in IC design implementation. Proficiency in EDA software from Synopsys and Cadence is helpful. Proficient users of Python, perl or TCL are also preferred.
If you have excellent English communication skills and are proficient in Perl, Python or TCL, you'll stand out from the crowd.
As an ASIC Physical Design Engineer at NVIDIA, you'll work with experts in all areas of physical design, driving physical friendly design with related teams. You'll work on the most advanced process/technology and the biggest chip in the world.