Description
We are looking for best-in-class STA (Static Timing analysis) Physical Design Engineers to join our outstanding Networking DFT team.
As a STA Engineer, you will be responsible for DFT STA execution, from RTL driven constraints and definitions through DFT constraints quality assurance to STA sign-off.
You will be part of a unique team of experts who have deep understanding in all aspects of pre and post silicon.
You will be exposed and work on a variety of challenging designs, unique DFT solutions that require deep silicon implementation understanding.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part in flows development.
Requirements:
- B.SC. in Electrical Engineering/Computer Engineering.
- 2-3 years of experience as STA engineer.
- Ability to quickly adapt to new technology and go deep into new areas.
- Strong communication skills.
- Great teammate.
- Drive new solutions based on any issues that arise.
Preferred qualifications:
- Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
- Knowledge in DFT flows such as ATPG, Mbist, Ijtag.
- Prior experience in DFT timing closures.
- Knowledge in CDC.
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
If you are a creative and autonomous engineer who loves a challenge, come and be part of the best physical design team in the industry!