Description
As a Senior DFT Verification Engineer at NVIDIA, you will be part of a team that is at the forefront of innovation in AI and accelerated computing. This role offers you the chance to contribute to groundbreaking projects while collaborating with highly skilled professionals in the industry.
Your primary responsibilities will include taking end-to-end ownership of DFX verification, pattern development, and silicon bring-up for a range of test features, including JTAG, boundary scan, security mechanisms, reliability tests, and test clocking across various test modes and ATPG configurations in multi-die environments.
You will work closely with various DFX teams, CAD, and methodology teams to improve flows and processes. Additionally, you will help develop and deploy DFT methodologies for our next-generation products.
In this role, you will have the opportunity to innovate and strive to improve the quality of DFT methods and AI deployment in the processes. You will also work with multi-functional teams to incorporate DFT features into the chip.
To succeed in this role, you should have a BSEE or MSEE from a reputable institution or equivalent experience with 3+ years of experience. You should be proficient in static timing analysis, ECO, ASIC/Logic Design Flow, HDL, and digital logic design. Experience in RTL and gates verification, simulation, and silicon bring-up is also required.
You should be familiar with BIST architecture and JTAG/IEEE1149.1/1500/1687/1838. Strong DFT knowledge in scan ATPG, compression techniques, and memory test is essential. Strong analytical and problem-solving skills with good scripting knowledge (either Perl/Python) are also necessary.