Description
You are someone who has traced the path from high-level design down to the bits that actually run on silicon, and you know that every line of compiler code can ripple through to the final chip. You thrive in large, layered codebases where data structures and algorithms are the difference between a tool that flies and one that crawls. You notice the subtle bugs that only show up in customer flows and you care enough to dig in until they are gone. You have written and maintained code that lives at the heart of EDA tools, and you know what it means to keep it efficient, reliable, and understandable by the next engineer. You are comfortable moving between C++ and C, sketching out a parsing routine, or optimizing a graph traversal. You like working with complex languages like Verilog and VHDL, and the challenge of keeping up with both the theory and the practical quirks of real-world RTL. You bring a methodical approach to profiling, testing, and documentation, because you know that’s how teams build tools that last. At Synopsys, your work will shape the FPGA flows that engineers around the world depend on.
Design, develop, troubleshoot, and maintain large-scale software systems for the RTL compiler stage of FPGA implementation and prototyping tools using C and C++. Write clear, detailed requirement and functional specifications that become the backbone for new features and system improvements. Build and optimize data structures and graph algorithms tailored for high-performance EDA workflows. Integrate advanced software engineering tools into your workflow, including static analysis, memory and runtime profiling, code coverage, and unit testing frameworks. Collaborate with the CAE team to plan and execute test strategies, and provide expert-level support to resolve customer issues. Maintain and enhance existing product features, ensuring robust performance and continuous reliability. Navigate and contribute to a complex design automation environment, balancing new development with legacy code stewardship.
Enable faster, more reliable FPGA prototyping for teams designing tomorrow’s chips. Reduce runtime and memory use in critical RTL compilation flows, letting customers handle larger, more complex designs. Improve code quality and maintainability, making it easier for future engineers to extend and support the toolset. Resolve customer-reported issues that directly affect tapeouts and time-to-market. Bring best practices in testing and documentation, raising the bar for engineering rigor across the team. Make complex HDL and RTL flows more accessible and robust for design engineers worldwide. Help Synopsys defend and extend its leadership in digital design automation.