Description
We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Your primary responsibility will be to drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
The ideal candidate will have a Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience) and shown knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools. You will also have understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure, experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools (i.e., Synopsys or Cadence) or in-house tools, background with logic synthesis at either block or full-chip level, at project execution and/or flow development, in-depth knowledge of industry standard EDA tools in related fields, and experience in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.
If you're creative and autonomous, we want to hear from you. You will also be eligible for equity and benefits.