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Synopsys

ASIC Physical Design Senior Engineer

Synopsys
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onsite senior full-time Yerevan

First indexed 13 May 2026

Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

We are seeking a skilled ASIC Physical Design Senior Engineer to join our team. As a senior engineer, you will be responsible for taking designs from netlist to GDSII, owning the full physical implementation flow for PHY, test chip, and subsystem-level blocks.

Key responsibilities include:

  • Building and optimizing floorplans, including power grid planning, pin placement, and macro positioning that set up the rest of the flow for success
  • Running placement, clock tree synthesis, and post-CTS optimization to meet timing, power, area, congestion, and signal integrity targets
  • Performing signoff-level timing analysis using PrimeTime, closing EMIR violations, and driving physical verification clean using ICV
  • Executing ECOs to resolve timing, power, or physical verification issues without destabilizing the design
  • Writing and maintaining Python, Tcl, Perl, or bash automation scripts to improve flow efficiency and reduce manual intervention

As a senior engineer, you will have the opportunity to work on complex projects and contribute to the development of new technologies and processes. You will also have the chance to mentor junior engineers and help shape the future of our organization.

Requirements include:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
  • Hands-on experience in ASIC physical design and implementation, taking designs through the full RTL to GDSII flow
  • Proficiency with Synopsys Fusion Compiler, ICC II, PrimeTime, and ICV, or equivalent industry-standard tools
  • Solid understanding of static timing analysis, including setup/hold closure, clock tree balancing, and multi-corner multi-mode constraints
  • Working knowledge of EMIR analysis and physical verification, including DRC, LVS, and antenna checks
  • Scripting ability in Python, Tcl, Perl, or bash, with experience using makefiles and version control systems like Git

If you are a motivated and experienced engineer looking for a challenging and rewarding role, please apply today.

This listing is enriched and indexed by YubHub. To apply, use the employer's original posting: https://careers.synopsys.com/job/yerevan/asic-physical-design-senior-engineer/44408/95049838752