Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
We are seeking an experienced RTL designer to join our team in Ho Chi Minh City. As an RTL Design Sr Staff Engineer, you will be responsible for designing and verifying DDRPHY/LPDDRR/HBM test chips using SystemVerilog/Verilog. You will also collaborate with analog and mixed-signal teams, automate workflows with scripting languages, debug complex hardware issues in lab bring-up and validation, document specifications and processes, and drive improvements in design and DFT/DFM flows.
Delivering reliable, high-speed memory IP for next-gen platforms, supporting rapid customer time-to-market, enhancing testchip team capabilities and innovation, mentoring and sharing expertise with peers, ensuring product quality through robust verification, and promoting a collaborative, learning-focused culture are some of the key responsibilities of this role.
To be successful in this position, you should have 6+ years of experience in RTL design/verification (SystemVerilog/Verilog), experience with high-speed interfaces (DDR/HBM preferred), skill in scripting (Python, Perl, Tcl, Shell), knowledge of ASIC/IP flows and DFT/DFM, and experience debugging complex hardware issues.
As a clear communicator and team player, analytical, proactive, and adaptable, open to learning and mentoring, you will thrive in this role.