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Synopsys

Staff ASIC Design Verification Engineer

Synopsys
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staff employee $98000-$147000 Nepean, Ontario

First indexed 18 Jun 2026

Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You will be a highly motivated and innovative Staff Digital Verification engineer, passionate about technology, driven by challenges, and eager to work on cutting-edge High-Bandwidth Memory (HBM) products. You bring a wealth of experience in digital verification, and you are proficient in System Verilog/UVM. You are a proactive problem-solver, capable of working independently and as part of a team, with the ability to network with senior internal and external personnel. Your excellent communication skills enable you to interact effectively with different design groups and customer support teams.

Responsibilities:

  • Verify ASIC RTL designs at both chip and block levels
  • Define and track verification test plans
  • Design and write constrained-random System Verilog testbenches using UVM (Universal Verification Methodology)
  • Create and examine Functional Coverage
  • Write System Verilog assertions
  • Debug Firmware, RTL and gate-level simulation failures
  • Bug Tracking using Software Tools such as Jira
  • Code Coverage Analysis

The Impact You Will Have:

  • Drive the development of high-performance, low-power silicon IP solutions
  • Enable faster time-to-market for differentiated products with reduced risk
  • Improve the functionality and performance of prototype test-chips through rigorous testing
  • Support the continuous innovation and technological advancement at Synopsys

Requirements:

  • BSEE or MSEE with a minimum of 2+ years of digital design/verification experience
  • Experience in writing testcases in System Verilog/UVM
  • Experience in debugging complex testbench and design related issues
  • Solid understanding of digital circuit design
  • Familiarity with scripting languages (Python or Perl)
  • Self-learner, independent, good organization and communication skills

Benefits:

  • Comprehensive medical and healthcare plans
  • Time away programs including ETO and FTO
  • Family support including maternity and paternity leave
  • ESPP (Employee Stock Purchase Plan)
  • Retirement plans
  • Competitive salaries
This listing is enriched and indexed by YubHub. To apply, use the employer's original posting: https://careers.synopsys.com/job/nepean/staff-asic-design-verification-engineer-17716/44408/96318863760