Description
We are looking for a Senior Physical Design Engineer to join our Networking Silicon engineering team. As a member of this team, you will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
Your daily work will involve all aspects of physical chip development (RTL2GDS) – trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.
To be successful in this role, you will need to have a successful track record of delivering designs to production, and be able to assist in design flow development and debugging, including application of ML/AI solutions.
You will also need to be a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
If you are a great teammate with strong analytical and debugging skills, and proficiency using Python, Perl, Tcl, Make scripting, we would love to hear from you.