ASIC Digital Design, Sr Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent over a decade building digital designs that ship in real products, not just pass verification. The kind of work where a timing closure mistake or a protocol misinterpretation costs months, and you have learned to catch those issues before they become problems. You think in micro-architectures, not just RTL. When you read a functional spec, you see the tradeoffs between area, power, and performance before you write a single line of SystemVerilog.

Responsibilities

• Architect and implement RTL designs for high-performance IP cores focused on die-to-die communication protocols including UCIe, targeting consumer and automotive applications
• Write micro-architecture documents that translate functional specifications into implementable design solutions for complex digital components, defining data paths, control logic, and interface behavior
• Own the full design flow from RTL coding in SystemVerilog through synthesis, CDC analysis, formal verification, and static timing closure using tools like Fusion Compiler
• Collaborate directly with the verification team to define testplans, close coverage gaps, and debug corner cases that surface during regression or customer testing
• Interface with customers to clarify specification ambiguities, align on design intent, and ensure the IP meets real-world integration requirements
• Mentor a distributed team of ASIC designers across multiple sites, reviewing code, guiding architecture decisions, and building technical depth in protocols and design methodology
• Drive quality processes including revision control with Perforce, scripting automation in Perl or Shell, and adherence to IP design standards for reuse and scalability

The Impact You Will Have

• Deliver production-ready IP cores that enable high-speed, low-latency die-to-die communication in next-generation automotive and consumer SoCs shipping to millions of devices
• Define architectural approaches for UCIe and related protocols that position Synopsys as a technical leader in chiplet and multi-die integration markets
• Reduce customer integration risk and time-to-market by delivering IP that meets timing, power, and area targets out of the box with minimal rework
• Elevate team capability across Noida and global sites by mentoring engineers on advanced RTL techniques, synthesis strategies, and protocol implementation best practices
• Influence product roadmaps and feature prioritization by providing technical feedback grounded in real silicon constraints and customer deployment scenarios
• Strengthen Synopsys IP quality reputation through rigorous design practices, comprehensive documentation, and proactive collaboration with verification and physical design teams
• Accelerate adoption of new design flows and tools like P&R-aware synthesis by piloting techniques and sharing learnings across the broader engineering organization

Requirements

• BSEE or MSEE in Electrical Engineering with 8+ years of hands-on experience in ASIC digital design and RTL implementation
• Deep expertise in at least one of the following protocols: UCIe, Ethernet, DDR, PCIe, CXL, or USB, with proven experience taking designs from architecture through silicon or customer delivery
• Strong command of micro-architecture definition, RTL coding in Verilog and SystemVerilog, and ASIC design flows including synthesis, CDC analysis, formal checking, and static timing analysis
• Hands-on experience with high-speed design considerations, P&R-aware synthesis techniques, and advanced EDA tools such as Fusion Compiler or equivalent
• Proficiency with revision control systems like Perforce and scripting languages such as Perl or Shell for automation and flow development
• Demonstrated experience technically leading and mentoring a team of ASIC designers, including code reviews, architecture guidance, and skill development
• Familiarity with IP design quality processes, reuse methodologies, and verification collaboration in multi-site or customer-facing contexts is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries