ASIC Verification Engineer

We are seeking an ASIC Verification Engineer to join our dynamic SoCV/Emulation Infrastructure and test-frameworks team.

The role involves building tools, infrastructure, and test frameworks for RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon. You will need to understand the Tegra system architecture, focusing on IPs in the SOC involved in boot and security features.

Key responsibilities:

• Develop tools that enable Design and Verification teams to access registers/memory/DMA engines and other features in their unit.
• Build features used for Silicon bring up, such as FUSE, ATE, Security, Flash/DMA, Board I2Cs, and USB debug devices.
• Assess and build C-model or RTL-simulation capability to simulate features before Silicon arrival in a pre-silicon environment.

Requirements:

• BS or MS in Computer Science or Electronics Engineering or equivalent experience with 0-2 years of experience.
• Strong programming skills in C, C++, and Python.
• Understanding of SOC and System Architecture.
• Knowledge of SOC devices like DMA, interrupt-engines, CPU, boot-devices, MMU/IOMMU.
• Experience with Operating System and Device-Driver concepts.

Preferred qualifications:

• Previous experience handling Silicon Bringup and enabling Emulation/FPGA related test frameworks.
• Exposure to Testbench architectures (C++ testbenches, SV/UVM based testbenches).
• Verilog and System Verilog coding skills are a plus.