CPU Verification Infrastructure Tools Architect

We are seeking a skilled Hardware and Software Developer to join our dynamic SoCV/Emulation Infrastructure and test-frameworks team.

The successful candidate will be responsible for designing and building tools, infrastructure, and test frameworks used in RTL-simulations, c-simulations, Emulation, FPGA, and on Silicon.

Key responsibilities include:

• Understanding Tegra system architecture, focusing on IPs involved in boot and security features
• Developing tools that enable Design and Verification teams to access registers/memory/DMA engines and other features in their unit
• Building C-model or RTL-simulation capability to simulate features before Silicon arrival in a pre-silicon environment
• Assessing and developing features used for Silicon bring-up, such as FUSE, ATE, Security, Flash/DMA, Board I2Cs, and USB debug devices

Requirements:

• BS or MS in Computer Science or Electronics Engineering with 5+ years of experience
• Strong programming skills in C, C++, and Python
• Understanding of SOC and System Architecture
• Knowledge of SOC devices, including DMA, interrupt-engines, CPU, boot-devices, and MMU/IOMMU
• Experience with Operating System and Device-Driver concepts, and ability to write no-OS test frameworks
• Strong software development skills, with a focus on scalability and maintainability

Preferred qualifications:

• Previous experience handling Silicon Bringup and enabling Emulation/FPGA-related test frameworks
• Exposure to Testbench architectures, including C++ testbenches and SV/UVM-based testbenches
• Verilog and System Verilog coding skills