Physical Design Power Integrity Engineer

We are looking for a best-in-class Physical Design Power Integrity Engineer to join our outstanding Networking Silicon engineering team. As a key member of our team, you will develop power integrity methodologies for complex/mixed designs, drive innovative solutions for advanced IR analysis and signoff required for NVIDIA chips, and own power integrity for sub-chip hierarchies.

Responsibilities:

• Develop power integrity (PI) methodologies for complex/mixed designs.
• Drive innovative solutions for advanced IR analysis and signoff required for NVIDIA chips.
• Own power integrity for sub-chip hierarchies.
• Contribute to flow development and methodology improvements.

Requirements:

• B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.
• 3+ years of experience in physical design.
• Proven experience in EMIR flows and methodologies.
• Knowledge in physical design flows and methodologies.
• Deep understanding of all aspects of Physical construction and Integration.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Great teammate.