Senior SOC Design Engineer - Networking Group

We are currently seeking an expert SOC Design and Integration Engineers with strong design fundamentals to work in Networking chip design group. You'll join a group of hardworking engineers to craft and implement the next generation innovative DPUs and Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing best high-speed communication devices, delivering the highest efficiency and lowest latency! The Networking Chip Design team in India is a new team which is growing at a fast pace.

Responsibilities:

• Understand all features of a given project and define project milestones based on internal roadmaps, assign them and track them through agile framework.

• Define and develop system-level methodologies, tools, and IPs to build subsystems in an efficient and scalable manner.

• Work with SOC Assembly team and drive cross-functional teams towards SOC milestone execution.

• Integrate all the pieces for a given defined project milestone and deliver the model to relevant teams for further verification at cluster/sub-system/SOC/emulation levels.

Requirements:

• BS (or equivalent experience) / MS with 4+ years of practical semiconductor design and architecture experience building complex SoC’s.

• Firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design.

• Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.).

• C/C++ programming or python or any other industry-standard scripting language experience desirable.

• Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling.

• Hands-on experience in successful tape-outs of multiple sophisticated, high-volume SoCs in advanced process nodes.

• Exposure to various Chip Design Functions to be able to collaborate and tackle sophisticated cross-functional problems.

• Excellent verbal and written communication skills to interact with cross-functional teams to build consensus.

• Experience in synthesis, physical design and DFT is a plus.

• Experience in RTL Build and Design Automation is a plus.

Preferred Qualifications:

• Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications.

• Experience in RTL coding and debug, as well as performance/power/area analysis and trade-offs.

• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.

• Prior experience of smartNIC and/or high-speed interconnects.

• Strong coding skills in Perl, Python, or other industry-standard scripting languages.