Description
We are seeking a Senior Physical Design Engineer to join our Networking Silicon engineering team. As a member of this team, you will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets. Your daily work will involve all aspects of physical chip development, including RTL2GDS, trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
The ideal candidate will have a BSEE/MSEE or equivalent experience, 3+ years of experience in VLSI physical design implementation on 5nm, 4nm, and 3nm technology, and strong analytical and debugging skills. They will also be proficient in Python, Perl, Tcl, and Make scripting, and have experience with CAD tools from Synopsys and Cadence.
As a Senior Physical Design Engineer, you will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly, and P&R, timing closure. You will also assist in design flow development and debugging, including the application of ML/AI solutions.
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.