Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You have spent years in the trenches of digital design where the difference between RTL that synthesizes cleanly and RTL that becomes someone else's nightmare is a decision you made on Tuesday. You know that writing Verilog is the easy part. The hard part is writing Verilog that closes timing, passes CDC without waivers, and does not make the implementation team want to rewrite your entire block.
You think about synthesis while you write RTL. Timing arcs are not abstract concepts, they are the reason you structured that state machine the way you did. When a design review surfaces a potential CDC issue, you are already three steps ahead, sketching the synchronizer and thinking through the corner cases. At Synopsys, you will work on real IP that ships in real products.
Design and implement RTL for digital blocks and subsystems in Verilog/SystemVerilog. Refine micro-architecture with focus on synthesizability, timing, testability, area, and power tradeoffs. Drive synthesis and front-end implementation activities. Support CDC/RDC/Lint signoff readiness and collaborate on design-quality closure. Work with implementation teams on STA fundamentals, timing constraints, and timing arc understanding. Collaborate with verification teams on functional debug, test planning, assertions, and coverage. Support debug and issue resolution using Verdi or similar debug tools. Participate in design reviews and help resolve integration and interoperability issues across product lines. Develop automation scripts for design, debug, reporting, and productivity.
Your RTL will directly influence the quality and time-to-market of Synopsys IP used by semiconductor companies worldwide. You will reduce iteration cycles between front-end and back-end teams by delivering synthesis-ready, timing-aware designs. Your collaboration will catch issues earlier, reducing costly respins and late-stage fixes. The automation you build will improve design productivity across multiple product lines. Your attention to CDC/RDC/Lint readiness will strengthen product quality and reduce signoff risk.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 4+ years of experience in digital design and/or RTL development. Practical knowledge of Verilog/SystemVerilog. Practical understanding of the ASIC design flow. Strong background in synthesis, front-end implementation, and design-for-closure methodology. Practical understanding of STA, timing constraints, and timing arcs. Experience with CDC/RDC/Lint concepts and signoff-ready design practices. Ability to collaborate effectively with verification, implementation, and validation teams. Scripting experience in Python, Tcl, Perl, or Shell. Strong communication and cross-team collaboration skills.