Senior Memory Controller Verification Engineer

We're seeking a hardworking and motivated Senior Verification Engineer to partner with design and architecture teams. You will craft and implement verification test plans, maintain regressions, close coverage, and sign off design or both functional correctness and performance expectations. This position offers a real impact on multiple product lines, including consumer graphics, self-driving cars, HPC, cloud computing, and AI!

Key Responsibilities:

• Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms)
• Craft and execute test plans for planned features
• Understand performance requirements and drive performance test plans
• Ensure code and functional coverage of all RTL
• Collaborate with FPGA and software teams to ensure software testing
• Plan for and participate in post-silicon verification and debug

Requirements:

• Bachelor's or Master's degree or equivalent experience
• 3+ years of ASIC verification experience with complex design units
• Experience with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Background with System Verilog and UVM-based methodology for ASIC verification

Nice to Have:

• Strong C/C++ programming experience
• Prior design or verification experience of dynamic memory controllers (DDR2, DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4, LPDDR5, LPDDR6)
• Strong debugging and problem-solving skills
• Scripting knowledge (Python, Perl, shell)
• Good interpersonal skills and ability to work as part of a team