Description
We are seeking an experienced R&D Engineering Manager to lead the physical implementation of PVT Sensor IP across the most advanced nodes in production. As a manager, you will be responsible for leading a team of ASIC physical design engineers, setting technical direction, reviewing work, and mentoring engineers through complex multi-corner, multi-mode closure challenges.
Key responsibilities include:
- Leading end-to-end physical implementation of PVT Sensor IP digital modules from floorplanning through GDSII across 1.4nm to 7nm foundry nodes, driving timing closure, power optimization, and sign-off
- Managing and growing a team of ASIC physical design engineers, setting technical direction, reviewing work, and mentoring engineers through complex multi-corner, multi-mode closure challenges
- Working hands-on when needed, jumping into critical path analysis, congestion fixes, or tricky STA scenarios to unblock your team and keep projects moving
- Collaborating daily with front-end design, verification, and product engineering teams to align RTL quality, design constraints, and implementation strategy from the start
- Owning project planning, resource allocation, and budget management for your team, balancing workload across multiple concurrent programs and node bring-ups
- Interface directly with customers to gather requirements, provide technical updates, resolve design issues, and ensure delivery meets their performance and schedule expectations
The ideal candidate will have 10+ years of experience in ASIC or IP physical design, with a proven track record of delivering complex designs at 7nm or below. You should have deep technical expertise across the full design flow from RTL to GDSII, including front-end understanding of synthesis and verification, and back-end mastery of STA, power analysis, and sign-off. Additionally, you should have direct experience managing and mentoring engineering teams, with a track record of developing engineers and delivering projects on time.
As a leader, you will shape the technical direction of physical implementation, drive continuous improvement in design flows using Synopsys EDA tools, and optimize methodology for faster convergence, better PPA, and cleaner handoffs to sign-off. You will also contribute to Synopsys IP portfolio competitiveness by ensuring every tapeout meets or exceeds PPA benchmarks and schedule commitments.