Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
You take pride in solving the toughest physical design problems, the kind where advanced nodes, tight margins, and complex IP all collide at once. You are the one who spots timing issues three weeks before they become fire drills and who automates flows so the team can actually sleep before tape-out. When a tool throws a curveball, you debug it, document what you learned, and share the fix. You like working across teams because you know every floorplan decision echoes through architecture, RTL, and circuits. If a macro placement looks clean on paper but causes IR drop issues two months later, you are the engineer who caught it early. You do not just want your work to close timing. You want it to ship, to matter, and to raise the bar for everyone who touches the design after you. At Synopsys, you will own the path from RTL to GDS and build IP that powers the next generation of semiconductor innovation.
Responsibilities
- Own and optimize the RTL-to-GDSII flow for UCIE IP, including floorplanning, place and route, timing closure, and signoff using PrimeTime, IC Compiler II, ICV, and RedHawk
- Integrate covercells, macros, and third-party IP blocks, ensuring clean abutment, proper power planning, and passing all QA checks
- Automate tool flows using Tcl and Python, debug complex physical design issues, and document best practices for reuse
- Collaborate with architecture, RTL, and circuit teams on test chip development, translating design intent into physical reality
- Prepare tape-out views, generate final documentation, and manage foundry design rule checklists through signoff
The Impact You Will Have
- Deliver high-quality, high-performance UCIE IP that meets aggressive power, performance, and area goals on advanced process nodes
- Eliminate late-stage surprises through robust flows and early issue detection that prevent costly respins
- Save your team hundreds of hours by automating repeatable tasks and sharing solutions that scale across projects
- Enable smooth integration for SoC teams who depend on your IP working correctly the first time
- Raise technical standards across multiple tape-outs, setting the example for what great physical design looks like
Requirements
- 5+ years of hands-on experience in block-level physical design, with exposure to advanced nodes such as 7nm or below
- Deep working knowledge of floorplanning, place and route, timing closure, IR-drop and electromigration analysis, and LVS/DRC signoff
- Strong proficiency with PrimeTime, IC Compiler II or Fusion Compiler, ICV, and RedHawk
- Proven experience integrating complex IP blocks and driving designs through tape-out
- Solid scripting skills in Tcl and Python for flow automation, experience with UCIE or die-to-die interconnect standards is a plus