Description
We are looking for a best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team. As a Physical Design Signoff CAD Engineer, you will develop physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs. You will work closely with block owners, full Chip STA engineers to assure high quality and timely convergence. Additionally, you will come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
Your responsibilities will also include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.
To succeed in this role, you will need a B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience) and 2+ years of fulltime relevant experience in the areas listed below. You will also need proven experience and strong knowledge in key technical domains, including: Physical Design, Backend CAD (Computer-Aided Design), STA (Static Timing Analysis) and Timing closure methodologies.
Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation) is also required. Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams are also essential.