Senior LPU ASIC Engineer

Join NVIDIA and become part of a team advancing the frontiers of AI technology! As we lead innovation in AI and accelerated computing, we seek a Senior LPU ASIC Engineer to contribute to our outstanding progress in chip design.

In the role of a Senior LPU ASIC Engineer, you will play a crucial role in our innovative LPU chip design.

Responsibilities:

• Full-Flow Ownership: Responsible for Synthesis, floorplanning, place & route, timing constraints, UPF and LEC at the block/partition level and top level.

• Cross-Functional Optimization: Partner with IP, Front-End logic design and Architecture teams to streamline IP integration, drive PPA (Power, Performance, Area) optimizations, resolving architectural bottlenecks to enable efficient physical implementation.

• Tapeout Execution: Lead design closure in collaboration with IP, PnR, Sign-off teams, ensuring 100% verification compliance for successful GDSII handoff and tapeout.

• Methodology Innovation: Architect data-driven EDA flows and methodologies in collaboration with CAD teams, implementing automated enhancements that measurably improve PPA and design cycle efficiency.

Requirements:

• B.S. in Electrical/Computer Engineering or equivalent experience (M.S./Ph.D. preferred) with 5+ years of industry experience delivering full-flow physical design for large-scale, high-performance SoCs at advanced process nodes.

• Full-Flow Execution: Proven track record of driving designs through the complete RTL-to-GDSII flow, including synthesis, placement, CTS, routing, extraction, and physical/electrical verification.

• Low-Power Expertise: Deep understanding of low-power design intent (UPF/CPF), formal equivalency checks (LEC), and rule verification for complex multi-voltage domain architectures.

• Clock & Timing Mastery: Expert-level proficiency in advanced CTS methodologies, clock tree synthesis, and sign-off timing analysis (MCMM STA) using complex constraints.

• PPA Optimization: Demonstrated ability to implement aggressive power, performance and area optimization techniques, and identify reduction opportunities across the entire physical design cycle.

• Sign-off & Integrity: Strong command of power grid design, EMIR analysis, and ECO generation to ensure robust silicon integrity and timing closure.

• DFT & Block-Level Integration: Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations.

• EDA Tool Proficiency: Expert-level command of industry-standard tool suites for end-to-end physical design flows.

• Automation & Innovation: Proficient in scripting (TCL, Python, Perl) to automate flows, with a forward-looking ability to integrate AI-driven optimizations for enhanced design efficiency.

• High-Speed IP Integration: Specialized experience in the physical design of blocks and partitions containing high-speed SerDes IPs, such as PCIe, CXL, C2C, and Die-to-Die interfaces a plus.