Description
Join an experienced testchip team developing in leading-edge technology. The group is designing DDRPHY/LPDDRR/HBM test chip and also includes HBM design/verification. You will join in the full silicon development flow including RTL design/verification/Synthesis/DFT/LAB bring-up etc.
Key qualifications include a history of excellent problem-solving skills, clear communication both written and oral, high-speed design and timing closure, designing RTL with SystemVerilog and Verilog, capable of automating repetitive tasks using a variety of scripting languages, 1+ years of experience in RTL design or verification, including interfacing with Mixed Signal Designs, interfacing with Analog and Mixed Signal designs, writing clear specification documents, experience of entire ASIC and IP development flow, aware of DFT/DFM flows, experience of debugging complex hardware issues.
Preferred experience includes interfacing with Mixed Signal Designs, capable of modeling Analog and Mixed Signal Circuits, capable of setting up and debugging physically aware synthesis, DDR and HBM DRAM technologies.