Mixed-Signal AMS Co-Simulation Verification Engineer

We are seeking a Mixed-Signal AMS Co-Simulation Verification Engineer to join our team. As a key member of our engineering team, you will be responsible for defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Exposure to Verilog/System Verilog and AMS concepts or circuit design (coursework, labs, or hands-on experience).

Why this matters

As a Mixed-Signal AMS Co-Simulation Verification Engineer, you will play a critical role in ensuring the quality and reliability of our high-performance SERDES and mixed-signal IP, which powers AI, automotive, cloud, and mobile applications at massive scale.