Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As an ASIC Digital Design Engineer, you will be part of a dynamic and diverse engineering team focused on subsystem and SoC-level verification. The team is committed to technical excellence, innovation, and continuous improvement, working collaboratively to deliver industry-leading solutions for Synopsys' global clients.
Responsibilities:
Develop and execute comprehensive verification plans for subsystem features and interfaces. Build, enhance, and maintain UVM-based verification environments for complex RTL designs. Create reusable and scalable testbenches, sequences, checkers, and scoreboards to ensure thorough coverage. Debug simulation failures, analyze waveform-level issues, and drive root-cause analysis to resolution. Collaborate closely with design, architecture, and cross-functional engineering teams to align on specifications and compliance. Define and implement test scenarios, including directed, constrained-random, and corner-case verification. Support regression planning, test execution, and coverage closure activities to ensure quality silicon delivery. Contribute to methodology improvements and best practices in functional verification. Communicate progress, technical findings, and risks effectively with stakeholders and team members.
Impact:
Enhance the robustness and performance of subsystem and SoC-level designs through rigorous verification processes. Drive the delivery of high-quality silicon solutions that power next-generation technologies. Accelerate time-to-market for Synopsys' clients by ensuring reliable and efficient verification workflows. Improve verification methodologies and contribute to best practices that set industry standards. Foster collaboration across design, architecture, and engineering teams to achieve common goals. Identify and resolve technical risks early, ensuring successful project outcomes and client satisfaction.
Requirements:
Bachelor's or Master's degree in electronics, electrical engineering, or a related field. Minimum 3+ years of hands-on verification experience, preferably in subsystem or SoC-level projects. Strong proficiency in protocols such as PCIe, CXL, UCIe, Ethernet, DDR, or USB. Solid experience with SystemVerilog/UVM and assertion-based verification techniques. Expertise in functional coverage, code coverage, and regression management. Strong debugging skills using simulation and waveform analysis tools. Exposure to formal verification techniques and their application in real-world scenarios.
Team:
You'll join a dynamic and diverse engineering team focused on subsystem and SoC-level verification. The team is committed to technical excellence, innovation, and continuous improvement, working collaboratively to deliver industry-leading solutions for Synopsys' global clients.
Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.