Description
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
We are seeking a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success.
As a Principal Simulation R&D Software Engineer, you will be responsible for designing, developing, and troubleshooting core algorithms for compiler. You will collaborate with local and global teams to enhance runtime performance for verilog compiler. You will engage in pure technical roles focused on software development and architecture. You will utilize your knowledge of digital simulation flows and EDA tools to drive innovation. You will leverage your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.
You will drive technological innovation in chip design and verification. You will enhance the performance and quality of simulation tools used globally. You will solve complex compiler optimizations problems to improve simulation performance. You will collaborate with cross-functional teams to achieve project milestones. You will pioneer new software architectures that set industry standards.
To succeed in this role, you will need strong hands-on experience in C/C++ based software development. You will require a deep understanding of design patterns, data structures, algorithms, and programming concepts. You will need knowledge of ASIC design flow and EDA tools and methodologies. You will require proficiency in Verilog, SystemVerilog, and VHDL HDL. You will need 10+ years of relevant EDA Software experience preferably in Simulation domain.