Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Senior ASIC Verification Engineer, you will be responsible for developing and executing comprehensive verification plans for complex ASIC designs, focusing on next-generation HBM (High Bandwidth Memory) products. You will write and maintain advanced testcases using SystemVerilog and UVM methodologies to ensure thorough coverage and robust verification.
You will also debug and analyze complex testbench and design-related issues, collaborating closely with design and mixed-signal engineering teams. Additionally, you will automate verification flows and processes using scripting languages such as Python or Perl to enhance productivity and coverage.
You will review and provide feedback on design specifications, contributing to architecture and design discussions to improve product quality. You will participate in code reviews, mentor junior engineers, and share best practices within the verification team.
You will document verification results, methodologies, and lessons learned to support knowledge sharing and process improvement.
The impact you will have includes accelerating the development of high-performance, reliable HBM solutions that power the next generation of computing and AI applications. You will ensure the delivery of robust, high-quality silicon products through meticulous verification and debugging.
You will drive innovation in verification methodologies and contribute to the continuous improvement of engineering processes. You will reduce time-to-market for cutting-edge products by identifying and resolving issues early in the design cycle.
You will enhance team capabilities by sharing knowledge, mentoring peers, and fostering a collaborative engineering environment. You will influence the direction of future product development by providing valuable insights into design and verification challenges.