Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
As a DFT Staff Engineer, you will own DFT tasks such as scan chain stitching, ATPG, and simulation. You will create timing constraints for mission and DFT modes, work with design and implementation teams, and support customer IP integration and silicon bring-up. You will also automate workflows with scripting and mentor junior team members.
The impact you will have is enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.
To succeed in this role, you will need a degree in Electronics, Electrical Engineering, or a related field. No DFT experience is required for junior roles, but 6+ years of experience is needed for senior roles. You should have knowledge of scan insertion, ATPG, JTAG, and experience with Synopsys tools such as Design Compiler, VCS, and TetraMAX. Scripting skills in Perl, TCL, or Python are also desirable.
You will be analytical, detail-oriented, proactive, collaborative, and communicative. You will be adaptable and eager to learn, with a passion for chip testability and reliability.