Principal ASIC Digital Design Engineer

As a Principal ASIC Digital Design Engineer, you will be responsible for designing and verifying advanced digital circuits for PAM-based SerDes PHY IP. Your expertise in high-speed serializer and data recovery circuits will position you as a key contributor to the next generation of PAM-based SerDes products.

What you'll do

• Designing and verifying advanced digital circuits for PAM-based SerDes PHY IP, ensuring robust and high-performance mixed-signal solutions.
• Developing RTL code, modeling analog blocks, and crafting complex system-level testbenches in Verilog to validate functionality and performance.

What you need

• Bachelor's or Master's degree in Electrical Engineering (BSEE or MSEE) with at least 10 years of industry experience in digital design and verification.
• Must be familiar with Verilog and VCS. Good knowledge of back-end synthesis tools DC/PT is required
• Must have knowledge of digital design methodologies, ATE production testing, DFT insertion, Synthesis constraints and flows