Description
You will conceptualize, design, and productize state-of-the-art RTL to GDS implementation for SLM monitors using ASIC design flows.
Design on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability.
Execute digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, and routing.
Drive post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure.
Perform physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff.
Collaborate with architects and circuit design engineering teams to create and refine new flows and methodologies.
Ensure pre-layout and post-layout timing closure and timing model characterizations across various design corners, meeting reliability and aging requirements for automotive and consumer products.
Accelerating the integration of next-generation intelligent in-chip sensors and analytics into Synopsys technology products.
Optimizing performance, power, area, schedule, and yield at every stage of the semiconductor lifecycle.
Enhancing product reliability and differentiation in the market, reducing risk for customers and partners.
Driving innovation in physical design, verification, STA, and signoff methodologies and tools.
Contributing to industry-leading SLM monitors and silicon biometrics solutions that set new standards.
Collaborating with cross-functional teams to ensure successful deployment and adoption of advanced technologies.