Description
You are a passionate, highly experienced layout design engineer who thrives at the intersection of technology leadership and hands-on technical execution. With a deep-rooted commitment to quality and innovation, you are adept at navigating the complexities of deep submicron CMOS, FinFET, and GAA process technologies. You possess a natural curiosity and drive to continuously learn, keeping yourself up to date with the latest industry advancements, particularly in advanced memory interface IP such as DDR and HBM.
As a leader, you are motivated by mentoring and elevating your team, fostering a collaborative environment that encourages knowledge sharing and accountability. You are comfortable handling multi-faceted projects, from initial floorplanning to the final tape-out, and you have a proven ability to manage schedules, estimate efforts, and deliver best-in-class products on time.
Your expertise spans across layout matching techniques, ESD protection, DFM, and advanced verification methodologies, enabling you to anticipate and solve complex challenges. You are recognised for your strong communication skills, both written and verbal, and you know how to clearly articulate technical concepts to cross-functional teams and customers alike.
You are inclusive, collaborative, and open-minded, actively seeking diverse perspectives while fostering a supportive team culture. You are accountable and results-driven, with a demonstrated ability to take ownership and deliver on commitments.
You will join a dynamic, high-impact team at the forefront of silicon IP innovation, dedicated to delivering world-class memory interface solutions. Our team thrives on technical excellence, close collaboration, and a shared commitment to pushing the boundaries of what's possible in chip design.