Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
We are looking for a passionate and highly skilled engineer who thrives in a collaborative, fast-paced environment. With a deep understanding of analog design principles, you have honed your expertise in static timing analysis (STA) and timing characterization over 4-8 years in the semiconductor industry. You are driven by curiosity and a desire to solve complex challenges, always seeking innovative solutions to enhance performance and reliability.
As a STA and Timing Characterization Specialist, you will be responsible for driving DDR, HBM, and UCIE timing generation and validation in partnership with circuit design and layout teams. You will perform static timing analysis (STA) and timing characterization, ensuring robust timing constraints and accurate correlation with design requirements. You will also debug and resolve timing violations at both circuit and system levels, applying deep transistor-level simulation expertise.
You will utilize SiliconSmart, NanoTime, and advanced scripting to automate timing analysis workflows and improve efficiency. You will collaborate closely with internal development teams to communicate findings, propose solutions, and implement best practices. You will provide technical leadership, mentoring junior engineers, and championing quality and accountability throughout project lifecycles.
As a member of our team, you will be empowered to drive innovation and technical excellence, contributing to Synopsys' global leadership in chip design and integration.