Description
Our organisation is seeking a passionate and experienced ASIC Digital Design Engineer with a strong background in design verification to join our Digital and Verification Development team.
As a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.
Key responsibilities include: Planning tests, checklists, coverage, and assertion planning. Creating detailed verification environments from functional specifications. Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. Writing test cases, checkers, and coverage that implement the verification test plan. Debugging simulations, including those of real signals modeled using SystemVerilog for analog. Performing RTL, GLS, and co-simulations and ensuring coverage closure. Participating in technical reviews and contributing actively. Providing customer support with the bring-up of IP in customer simulation environments. Following and improving development processes to ensure high-quality output.
Requirements include: BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 2+ years of experience in design verification. Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.
Ideal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written. A great team player, willing to support others. Self-motivated and highly enthusiastic about technology and solving problems.