Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As a Sr Staff Engineer in SOC Engineering, you will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. You will execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.
Key Responsibilities:
- Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)
- Execute synthesis, place & route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets
- Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities
- Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence
- Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions
- Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency
Key Requirements:
- Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field
- 5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm)
- Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place & route, CTS, timing optimization, STA, EMIR, and physical verification
- Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime
- Strong scripting and automation skills using Python, PERL, TCL, or similar languages
- Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs
- Exposure to high-frequency design and low-power design methodologies
Benefits:
- Comprehensive medical and healthcare plans that work for you and your family
- In addition to company holidays, we have ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.