Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
We are seeking a passionate and innovative Staff Engineer who thrives on turning complex technical challenges into industry-leading solutions. You will lead the design and development of next-generation DDR and HBM PHY IP layout, driving technical innovation and best practices. You will also provide technical mentorship and guidance to junior engineers, fostering skill development and knowledge sharing across the team.
As a Staff Engineer, you will take ownership of layout planning, execution, and quality review processes to ensure on-time delivery of high-quality silicon IP. You will collaborate with cross-functional teams, including circuit design, verification, and product engineering, to meet project goals and customer requirements. You will also manage effort estimation, project scheduling, and execution in multi-disciplinary team settings.
The successful candidate will have a strong command of deep submicron effects, advanced floorplan techniques, and process technologies such as CMOS, FinFET, and GAA. You will also have expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and bond-pad/IO frame design.
If you are a proactive problem solver, ready to lead, mentor, and make a tangible impact in a dynamic, fast-paced environment, we encourage you to apply for this exciting opportunity.