Description
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
You are a dynamic engineer with working experience in RTL implementation, DFT/BIST, verification, flow automation, and understanding of hierarchical SoC architectures and IEEE1149/1500 and 1687 standards and pattern porting. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them in our premier customer base.
What You'll Be Doing:
- Working closely with a world-class R&D team, you'll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) built over a robust DFT framework.
- Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.
- Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.
- Driving the deployment and smooth execution of SLM and Test solutions into customers' projects.
- Enabling customers to realize the value of silicon health monitoring using a robusta DFT framework throughout the lifecycle of silicon bring-up, validation, through in-field operations.
The Impact You Will Have:
- Enhancing Synopsys' Silicon Lifecycle Management (SLM) and DFT IP portfolio and end-to-end solution.
- Driving the adoption of Synopsys' SLM and DFT solutions at premier customer base worldwide.
- Influencing the development of next-generation SLM IPs and solutions.
What You'll Need:
- BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field.
- 8 years of hands-on experience with DFT/BIST insertion, RTL design, and functional verification.
- Good exposure to JTAGIEEE 1149.1, IEEE 1687/1500, Testdata access mechanism.
- Knowledge on memory defectivities soft errors and reliability.
- Familiarity with error correcting codes such as Hamming and Hsiao.
- Hands-on experience in dealing with hierarchical SoCs, 1149.1/1500/1687 standards and pattern porting.
- Familiarity with either Synopsys TestMAX Tool chain or competitive offerings.
- Debugging abilities to identify and resolve issues in functional verification in UVM environment.
- Hands on experience in flow automation.
- Knowledge of Synthesis is a must with understanding of timing constraints (SDC).
- Knowledge of Lint, CDC, RDC is a plus.
- Knowledge of physical implementation is not a must, but good to have.
- Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions.
- Customer facing experience is a plus – educating/guiding customer on technical details of a solution.
- Good to have:
- Hands-on bring-up and debug experience of silicon is a plus.
- Architecture/micro-architecture experience.
- Understanding of GenAI and Agentic AI workflows.