Description
Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
As an ASIC Physical Design Senior Manager, you will lead the end-to-end physical implementation of test chips across multiple advanced foundry nodes (2nm–7nm), ensuring timely and high-quality project delivery. You will manage, mentor, and develop a multidisciplinary team of ASIC physical design engineers, fostering a culture of technical excellence and collaboration.
Key responsibilities include:
- Leading cross-functional teams to drive seamless project execution from RTL to GDSII
- Overseeing project planning, resource allocation, and team budgeting to align with organizational goals and customer requirements
- Interfacing directly with customers and stakeholders to gather requirements, provide status updates, and ensure satisfaction throughout the project lifecycle
- Driving continuous process improvement, leveraging expertise in Synopsys EDA tools to optimize design flows and achieve best-in-class PPA and sign-off metrics
As a leader, you will play a key role in shaping the team's technical direction, fostering collaboration, and driving excellence in every project.
Rewards and benefits include comprehensive health, wellness, and financial benefits, including competitive salaries, ESPP, and retirement plans.