Description

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We are seeking an experienced IC physical design expert to lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.

Responsibilities

Technically lead and manage local and remote teams for complex Subsystem designs digital implementation and signoff.
Guide signoff quality timing constraints development and qualification for critical Subsystem designs with hundreds of clocks.
Drive PNR flow and methodology for timing critical muti-million deep sub-micro designs flat/hierarchical digital implementation.
Handson expertise in all aspects of flat, hierarchical PNR implementation tasks like synthesis, floorplanning, design partitioning, DFT, low power/UPF based implementation, timing constraints, clock tree synthesis, routing and optimization, extraction, timing signoff, signal integrity, physical verification, Power & IR drop signoff to debug and resolve critical implementation bottlenecks.
Requires close interaction and collaborative teamwork with multiple functional groups front end, analog, PM/PEMs.
Drive RTL, design partitioning, timing constraints related feedback to Frond-end team for data path optimization, clock & reset architecture improvements for enabling high speed timing closure, PPA improvements.

Requirements

MS in Electrical Engineering; 10+ years in physical design, static timing analysis.
Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
Must have experience in leading and managing local, remote implementation teams.
Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
Strong scripting and software skills.

What You'll Need

Inclusive leader and effective communicator.
Innovative, collaborative, and quality-driven.
Thrives in dynamic environments.

The Team You'll Be A Part Of

Join a global engineering team advancing high-speed silicon IP design. We value innovation, inclusion, and technical excellence.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more details about salary and total rewards during the process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

### Time Away

In addition to company holidays, we have ETO and FTO Programs.

### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

What You'll Be Doing

Deliver signoff-quality, high-performance silicon solutions.
Mentor and develop engineering teams.
Drive process improvements and technical innovation.
Enhance Synopsys’ leadership in high-speed IP.
Facilitate successful cross-team collaboration.
Enable next-generation chip architectures.

The Impact You Will Have

Deliver signoff-quality, high-performance silicon solutions.
Mentor and develop engineering teams.
Drive process improvements and technical innovation.
Enhance Synopsys’ leadership in high-speed IP.
Facilitate successful cross-team collaboration.
Enable next-generation chip architectures.

What You’ll Need

MS in Electrical Engineering; 10+ years in physical design, static timing analysis.
Must Have- SOC Physical Desing Engineer with hands on experience in STA, Timing Constraints development & qualification
Hands-on RTL-GDSII physical implementation tapeout experience for complex high-speed flat/hierarchical designs.
Must have experience in leading and managing local, remote implementation teams.
Expertise of the Synopsys tools, flows and methodologies required to execute physical design projects.
Strong scripting and software skills.

Who You Are

Inclusive leader and effective communicator.
Innovative, collaborative, and quality-driven.
Thrives in dynamic environments.

The Team You’ll Be A Part Of