Description
We are seeking an experienced Application Engineer to join our Physical Verification team. As a Staff Engineer, you will be responsible for developing and validating DRC, LVS, and Fill runsets for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.
Your primary focus will be on collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. You will also be responsible for automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.
In addition, you will troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. You will interface directly with customers and Field Application Engineers (FAEs) to gather requirements, provide technical support, and ensure successful deployment of PV solutions.
As a natural collaborator and mentor, you will guide junior team members and foster a supportive team environment. Your excellent communication skills will enable you to engage confidently with customers and FAEs, translating complex requirements into innovative solutions.
Key Responsibilities:
- Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool
- Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes
- Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python
- Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges
- Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions
- Mentor junior team members and foster a supportive team environment
Requirements:
- B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field
- 5-8 years of hands-on experience in the Physical Verification (PV) domain
- Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS
- Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development
- Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements
- Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks
- Exposure to competitive EDA tools and awareness of their strengths and limitations
Ideal Candidate:
- Analytical thinker with strong problem-solving abilities and meticulous attention to detail
- Collaborative team player who fosters knowledge sharing and mentorship
- Effective communicator, capable of translating technical concepts to diverse audiences
- Adaptable and proactive, with a passion for continuous learning and innovation
- Customer-focused, with a commitment to delivering high-quality solutions on time
- Self-driven, organized, and able to manage multiple priorities in a fast-paced environment
Experience Level: senior Employment Type: full-time Workplace Type: onsite Category: Engineering Industry: Technology Salary Range: Not stated Salary Min: Not stated Salary Max: Not stated Salary Currency: USD Salary Period: year Required Skills: IC Validator, Calibre, Pegasus, Perl, Tcl, Python, CMOS layout, ASIC design flows, foundry process requirements Preferred Skills: None