ASIC Digital Design, Senior Staff Engineer

We are seeking a highly skilled ASIC Digital Design, Senior Staff Engineer to join our team. As a Senior Staff Engineer, you will be responsible for developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.

What you'll do

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in SystemVerilog and Verilog for RTL development.