Low Power Verification Applications Engineer

You will be a Low Power Verification Applications Engineer at Synopsys, working with semiconductor companies to solve low power verification challenges.

As a Low Power Verification Applications Engineer, you will partner directly with semiconductor companies across the region to solve low power verification challenges including power estimation, reduction, audit, correlation, and efficiency analysis.

You will deploy and optimize Synopsys low power tools like PrimePower-RTL, SpyGlass-Power, VC LP, and PTPX across customer design flows, working at both RTL and netlist levels.

Your responsibilities will also include:

• Debugging power reports, analyzing power matrices, and tracing issues through UPF, RTL, and gate-level designs to resolve discrepancies and improve accuracy
• Collaborating with Synopsys R&D and product validation teams to develop methodologies that address customer-specific problems and feed real-world requirements back into product roadmaps
• Building and maintaining automation scripts in TCL, Perl, and Unix shell to streamline power analysis workflows and improve turnaround time for customer engagements
• Coordinating with technical account managers and worldwide account teams to shape customer strategies, drive tool adoption, and support successful project completion
• Gathering, refining, and tracking flow requirements based on customer feedback, engineering judgment, and emerging tool capabilities

The impact you will have includes:

• Enabling semiconductor companies to meet aggressive power budgets and ship complex chips on schedule by solving power verification bottlenecks they cannot resolve alone
• Influencing the direction of Synopsys low power tools by bringing real customer pain points and use cases directly to R&D teams
• Building repeatable, scalable low power methodologies that become the foundation for how customers verify power across multiple projects and product lines
• Accelerating customer adoption of Synopsys solutions, directly contributing to business growth and long-term account relationships in the region
• Reducing customer design respins by catching power issues earlier in the flow, saving months of schedule and significant engineering cost
• Establishing yourself as a trusted technical advisor to design teams, the person they call when power verification gets hard
• Shaping how the next generation of AI, mobile, and automotive chips are designed by helping customers optimize power at every level of the design hierarchy

To be successful in this role, you will need:

• BE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 3-5 years of hands-on industry experience in ASIC design or verification
• Deep working knowledge of low power verification including power estimation, reduction techniques, power exploration, audit, efficiency analysis, power-load models, memory power analysis, LP simulation, LP linting, and HW/emulation cycle-based power profiling and correlation
• Proven experience with Synopsys low power tools such as PrimePower-RTL (logical and physical mode), SpyGlass-Power, VC LP, PTPX/PrimePower, or RTL Architect (PPA), or equivalent industry-standard LP signoff tools
• Strong command of VHDL, Verilog, and SystemVerilog RTL, and solid understanding of ASIC design flows from RTL to tapeout
• Hands-on experience debugging power reports and matrices at RTL and netlist levels, and working with UPF for low power verification
• Advanced scripting skills in TCL, Unix shell, Perl, or Python for automation, flow development, and debugging
• Experience with glitch power analysis and power correlation across RTL, gate-level, and emulation environments is a strong plus

In return, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.