Principal Engineer - ASIC Digital Design (Memory Interface IP- HBM/DDR/LPDDR)

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years designing ASICs that move data at speeds most people cannot fathom, and you understand that memory interface IP is where performance lives or dies. HBM, DDR, LPDDR are not just acronyms to you, they are architectures you have debugged at 2 a.m., optimized for power and timing, and shipped into production silicon that someone is using right now.

What You'll Be Doing

• Design and own complex RTL blocks for HBM, DDR, and LPDDR memory interface IP, from architecture through implementation and verification handoff
• Collaborate directly with analog design teams to define and validate mixed-signal interfaces, ensuring timing closure and signal integrity across the full IP stack
• Develop and execute detailed verification plans in partnership with the verification team, including corner case analysis and protocol compliance testing
• Drive timing, power, and area optimization using industry-standard EDA tools like Synopsys Fusion Compiler, PrimeTime, and DC Compiler
• Lead technical reviews and design audits, providing clear direction on architecture tradeoffs and implementation risks
• Mentor engineers on the team, reviewing RTL code, guiding design decisions, and helping them build the judgment that separates working designs from great ones
• Interface directly with customer engineering teams to debug integration issues, answer technical questions, and ensure successful IP deployment in their SoCs

The Impact You Will Have

• Deliver memory interface IP that enables customers to hit their performance and power targets in AI, automotive, and data center applications
• Reduce integration risk and time-to-market for customers by designing IP that works correctly the first time in silicon
• Set the technical standard for RTL quality, verification rigor, and design methodology across the IP development team
• Solve hard problems at the boundary of digital and analog design that directly affect whether a multi-billion transistor chip tapes out on schedule
• Build the next generation of design talent at Synopsys by mentoring engineers and raising the bar on what good design looks like
• Contribute to Synopsys' position as the go-to provider for high-speed memory interface IP in the most demanding applications on the planet
• Shape the roadmap for future memory interface IP by bringing deep technical insight from customer engagements and silicon bring-up back into the product

What You'll Need

• 8 - 10+ years of hands-on ASIC digital design experience with a strong focus on RTL design and verification
• Deep expertise in at least two of the following memory interface protocols: HBM, DDR4, DDR5, LPDDR4, LPDDR5
• Proven experience designing and delivering production-quality IP or SoC blocks that have taped out and been validated in silicon
• Strong command of SystemVerilog for RTL design and familiarity with UVM or other verification methodologies for cross-functional collaboration
• Experience working with AMBA protocols (AXI, AHB, APB) in the context of memory subsystem integration
• Proficiency with Synopsys or Cadence EDA toolchains for synthesis, timing analysis, and power optimization
• Experience with mixed-signal interface design and collaboration with analog teams is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries