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From the employer's careers site First seen 7 Nov 2026

FPGA Engineer

Cisco San Jose, California On-site senior full-time

Salary

$154,900 to $225,300 per year

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Description

The Network Hardware Engineering group (NHE) at Cisco designs complex next-generation Data Center switching products. As a FPGA Engineer, you will serve a range of roles, from IP creator and architect to solution integrator, guiding solution verification and ensuring products meet Cisco and industry quality standards.

Responsibilities:

  • Drive innovation in FPGA design, RTL development (Verilog/SystemVerilog), FPGA architecture, synthesis, timing closure, simulation, verification, and hardware lab debugging.
  • Work cross-functionally with system designers, diagnostics engineers, customer escalation engineers, and external vendors to ensure robust test methodology and timely issue mitigation.
  • Work independently using best practices with minimal guidance and direction.

Minimum Qualifications:

  • Bachelor’s degree in electrical engineering with 7+ years of relevant experience or master’s degree in electrical engineering with 4+ years of relevant experience.
  • Experience in full-lifecycle FPGA design.
  • Experience writing structured, reusable, and optimized Verilog.
  • Expertise with vendor toolchains, such as Vivado, Quartus or Libero.
  • Experience with timing closure and writing timing constraints.
  • Experience with lab work using tools such as oscilloscopes, logic analyzers, programming dongles and their SW apps.

Preferred Qualifications:

  • Comfortable working in a Linux environment.
  • Experience with scripting languages - shell, python, Tcl etc.
  • Experience writing test benches or running simulations.
  • Has worked with more than one FPGA vendor.
  • Previous experience with schematic design or system design.

Benefits:

  • Medical, dental and vision insurance.
  • 401(k) plan with a Cisco matching contribution.
  • Paid parental leave.
  • Short and long-term disability coverage.
  • Basic life insurance.
  • 10 paid holidays per full calendar year.
  • 1 paid day off for employee’s birthday.
  • Paid year-end holiday shutdown.
  • 4 paid days off for personal wellness.
  • 16 days of paid vacation time per full calendar year for non-exempt employees.
  • Flexible vacation time off program for exempt employees.
  • 80 hours of sick time off provided on hire date and each January 1st thereafter.
  • Optional 10 paid days per full calendar year to volunteer.

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Skills

Required

  • FPGA design
  • RTL development
  • Verilog
  • SystemVerilog
  • FPGA architecture
  • synthesis
  • timing closure
  • simulation
  • verification
  • hardware lab debugging
  • Vivado
  • Quartus
  • Libero
  • timing constraints
  • lab work
  • oscilloscopes
  • logic analyzers
  • programming dongles

Nice to have

Ready to apply?

You apply with the employer directly. Their original posting is here: https://cisco.wd5.myworkdayjobs.com/en-US/Cisco_Careers/job/San-Jose-California-US/Senior-FPGA-Engineer_2027589

Apply on Cisco