Principal Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

You will be a Principal Digital Verification Engineer at Synopsys, leading the verification of Memory Interface IP, including HBM, DDR, and LPDDR.

Job Overview As a Principal Digital Verification Engineer, you will design and build verification environments for Interface IP protocols including HBM, DDR, LPDDR, and AMBA using SystemVerilog and UVM.

Key Responsibilities

• Design and build verification environments for Interface IP protocols
• Write detailed test plans covering functional scenarios, corner cases, and protocol compliance
• Develop reusable verification IP and testbenches adaptable across multiple projects and IP variants
• Collaborate with design and architecture teams to identify bugs and close coverage gaps
• Run functional coverage analysis and drive coverage closure
• Mentor junior verification engineers on UVM best practices and verification strategy
• Use simulation tools like VCS or ModelSim to execute regression suites and debug failures

Requirements

• Bachelor's or Master's in Electrical Engineering or Computer Engineering
• 8-10+ years of hands-on ASIC or SoC verification experience
• Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA
• Strong proficiency in SystemVerilog and UVM
• Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture

Benefits

• Comprehensive medical and healthcare plans
• Time away programs, including ETO and FTO
• Family support, including maternity and paternity leave
• ESPP, allowing purchase of Synopsys common stock at a 15% discount
• Retirement plans varying by region and country
• Competitive salaries