Description
We are seeking an innovative CAD Software Engineer with particular interest in strategies and algorithms for large scale RTL quality, timing, and power optimization. Our team develops these tools by fusing advances in parallel computing, machine learning, and novel algorithms in C++.
In this role, you will be responsible for inventing new methods to enable parallel, graph-based RTL traversal, analysis, and manipulation. You will also devise strategies for rapidly analyzing the impact of RTL changes on data path latency, power, and impact to DFT, clocking, and power delivery.
Requirements:
- MS or PhD in Electrical Engineering or Computer Science or equivalent experience
- 3+ years of relevant experience in CAD software and VLSI hardware design
- Demonstrated ability in software development with C++, particularly in algorithm development related to graph traversal, pattern matching, and optimization
- Familiarity with RTL design, including Verilog and SystemVerilog code, as well as general hardware design concerns such as scan chain insertion, MBIST, clock and power distribution, and bus architectures
- Familiarity with related EDA techniques, including logic synthesis, global route, static timing analysis, and SAT solvers
- Strong communication and interpersonal skills
Preferred qualifications include experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization. Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc. is also desired.