Description
You will work as a Field Application Engineer, Verification at Synopsys, a leading provider of engineering solutions from silicon to systems.
Your role involves working directly with semiconductor design teams across the region to deploy and optimize Synopsys verification solutions, including VC SpyGlass, VCS, VC LP, VC Formal, and Verdi.
Key responsibilities:
- Debug complex RTL signoff issues in customer designs, such as CDC violations, lint errors, RDC problems, low power UPF conflicts, and formal property failures.
- Partner with Synopsys R&D and product validation teams to develop new flows, reproduce customer issues, and drive tool enhancements.
- Lead technical engagements during critical project phases, onsite or remote, ensuring customers hit their verification milestones and tapeout schedules.
- Gather requirements from customer feedback and design challenges, translate them into flow improvements, and work with product teams to prioritize and track delivery.
- Coordinate with account managers and technical account managers to shape customer strategies, drive tool adoption, and support business growth.
- Train customer engineering teams on verification methodologies, tool usage, and best practices.
The impact you will have:
- Enable customers to close CDC, lint, and low power signoff weeks or months faster.
- Reduce customer respins by catching critical RTL issues early.
- Drive adoption of Synopsys verification tools across new projects and teams.
- Influence Synopsys product roadmaps by surfacing real customer pain points.
- Build repeatable flows and reference methodologies that scale across multiple customer projects.
Requirements:
- BE/BTech/ME/MTech in Electronics Engineering, Computer Science, or Microelectronics with 3-5 years of hands-on industry experience in ASIC design or verification.
- Strong command of VHDL, Verilog, and SystemVerilog RTL.
- Proven experience with RTL signoff flows, including linting, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and property checking.
- Hands-on work with low power verification techniques using UPF or CPF.
- Exposure to simulation and verification methodologies.
- Working knowledge of Synopsys EDA tools such as VC SpyGlass, VCS, VC LP, VC Formal, FishTail, or Verdi.
Rewards and benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.