RTL Design, Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You have spent years designing RTL that ships in real products, not just passes verification. You know that the difference between a design that meets timing at 800MHz and one that barely scrapes by at 600MHz is a hundred small decisions made during architecture, and you are the kind of engineer who makes those decisions deliberately. You think in trade-offs, area versus latency versus throughput, and you can articulate why you chose one path over another without needing to defend it.

Responsibilities

• Design and architect next-generation high-performance RTL for DesignWare IP cores targeting commercial, enterprise, and automotive applications
• Translate IEEE 802.3 specifications and customer requirements into detailed micro-architecture documents and synthesizable Verilog or SystemVerilog RTL
• Own RTL implementation end to end, including coding, synthesis with Fusion Compiler or similar tools, CDC analysis, formal verification, and timing closure at speeds exceeding 600MHz
• Build complex datapath architectures such as Reed Solomon FEC encoders and decoders, BCH codes, parallel CRC engines, and MAC SEC blocks with clear area, latency, and throughput trade-offs
• Debug and resolve design issues across lint, CDC, synthesis, and static timing flows using industry-standard tools
• Collaborate with global teams of designers, verification engineers, and customers to refine specifications, resolve technical challenges, and deliver production-quality IP
• Mentor and technically lead a small team of designers, reviewing their work and guiding architecture decisions

The Impact You Will Have

• Your RTL designs will ship in high-volume products across automotive, enterprise, and commercial markets, directly affecting performance and reliability
• You will define micro-architectures that set the standard for area efficiency, timing closure, and power consumption in next-generation DesignWare IP
• Your ability to close timing at high frequencies will enable customers to meet aggressive performance targets in their SoCs
• Your architectural decisions will influence how DesignWare IP scales across protocol generations, from Ethernet to PCIe to MIPI
• Your mentorship will elevate the technical capabilities of the design team and improve the quality of deliverables across the board
• Your collaboration with customers will ensure that Synopsys IP meets real-world requirements, not just spec checkboxes
• Your contributions to design flows, synthesis methodologies, and quality processes will strengthen the entire IP development pipeline

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics, or VLSI with 5 to 10 years of hands-on RTL design experience
• Proven track record designing datapath blocks such as Reed Solomon FEC, BCH codes, parallel CRC, or MAC SEC engines with demonstrable trade-offs in area, latency, and throughput
• Deep experience with synthesizable Verilog or SystemVerilog RTL coding for ASIC designs, including lint, CDC, synthesis, and formal verification flows
• Hands-on experience closing timing on designs running at 600MHz or higher, ideally using physical-aware synthesis tools like Fusion Compiler
• Strong knowledge of at least one industry protocol: Ethernet, DDR, PCIe, USB, MIPI, or AMBA (AXI, AHB)
• Experience with control path designs such as asynchronous FIFOs, DMA architectures, and SPRAM or DPRAM interfaces
• Familiarity with Perforce or similar version control systems and scripting in Perl or shell is a plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• In addition to company holidays, we have ETO and FTO Programs
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• Purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Save for your future with our retirement plans that vary by region and country
• Competitive salaries