Description
You will be a Sr. Staff Digital Verification Engineer at Synopsys, working on Memory Interface IP, specifically HBM, DDR, and LPDDR.
You have spent over a decade verifying complex ASIC designs and have extensive experience with memory interfaces, including HBM, DDR, and LPDDR.
Your responsibilities will include:
- Designing and building verification environments for Interface IP protocols using SystemVerilog and UVM
- Writing detailed test plans that cover functional scenarios, corner cases, and protocol compliance
- Developing reusable verification IP and testbenches that can be adapted across multiple projects and IP variants
- Working directly with design and architecture teams to identify bugs and close coverage gaps
- Running functional coverage analysis and driving coverage closure
- Mentoring junior verification engineers on UVM best practices and verification strategy
You will need:
- A Bachelor's or Master's in Electrical Engineering or Computer Engineering with 6 to 8+ years of hands-on ASIC or SoC verification experience
- Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production-level designs
- Strong proficiency in SystemVerilog and UVM
- Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture
The team you will be part of is highly skilled and motivated, focused on delivering cutting-edge Interface IP solutions.
Rewards and benefits include comprehensive medical and healthcare plans, time away programs, family support, ESPP, retirement plans, and competitive salaries.