Layout Design, Staff Engineer

Overview

You will be part of Synopsys, the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products.

Job Description

You have spent years in the trenches of custom layout, working at process nodes where a misplaced contact or a floorplan decision made too quickly shows up months later in silicon. You know that great layout is not just about passing DRC and LVS, it is about understanding how electrons actually move through metal stacks at 7nm and below, and designing for that reality.

Responsibilities

• Lead layout development for cutting edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies
• Own floorplanning, layout matching, ESD design, latch-up mitigation, and DFM compliance for analog and mixed-signal blocks that have to work in silicon
• Drive layout reviews, quality checks, PERC and EMIR analysis, and release processes that meet both internal standards and customer requirements
• Mentor junior layout engineers through hands-on technical leadership, teaching them how to solve real problems in deep submicron design
• Collaborate with cross-functional teams including analog designers, verification engineers, and foundry partners to meet project timelines and deliver best-in-class IP
• Estimate effort, plan schedules, and execute layout projects in a multi-site, cross-functional environment where dependencies are real and deadlines matter
• Support critical customer-facing layout requirements including bond-pad layout, IO frame design, pitch requirements, and LEF generation

The Impact You Will Have

• Your layout work will directly enable next generation memory and interconnect IP that ships in high-performance SoCs across AI, automotive, and data center applications
• The floorplans and matching techniques you develop will set the standard for signal integrity and power efficiency in PHY designs at 7nm and below
• Your mentorship will build a stronger layout team capable of executing complex projects with less rework and higher quality
• The processes you establish for layout reviews, EMIR analysis, and release will reduce time-to-market and improve first-pass silicon success rates
• Your collaboration with foundry partners will help Synopsys stay ahead on emerging process technologies and design rule changes
• The IP you deliver will help customers integrate more memory bandwidth and interconnect capability into their SoCs with reduced risk
• Your technical leadership will shape how Synopsys approaches layout for the next wave of DDR, HBM, and UCIe standards

Requirements

• BTech or MTech in Electronics Engineering, VLSI, or related field
• 5+ years of hands-on layout design experience in analog, mixed-signal, or PHY IP development
• Deep understanding of deep submicron effects and proven experience with FinFET and GAA process technologies at 7nm and below
• Expertise in layout matching techniques, ESD design, latch-up mitigation, PERC, EMIR analysis, DFM, and LEF generation
• Demonstrated ability to lead layout projects from floorplan through release, meeting quality and schedule commitments
• Experience with bond-pad layout, IO frame design, and pitch requirements for high-speed interfaces
• Understanding of PHY level customer requirements and how layout decisions affect system-level performance is a strong plus

Benefits

• Comprehensive medical and healthcare plans that work for you and your family
• Time away: company holidays, ETO and FTO Programs
• Family support: maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP: purchase Synopsys common stock at a 15% discount, with a 24-month look-back
• Retirement plans: save for your future with our retirement plans that vary by region and country
• Competitive salaries