Sr. Staff Digital Verification Engineer (Memory Interface IP- HBM/DDR/LPDDR)

You will be a Sr. Staff Digital Verification Engineer at Synopsys, working on Memory Interface IP protocols including HBM, DDR, LPDDR, and AMBA.

You have spent the better part of a decade verifying complex ASIC designs, and you know that the hardest bugs are the ones that hide in corner cases three layers deep in a protocol handshake.

Your responsibilities will include:

• Designing and building verification environments for Interface IP protocols using SystemVerilog and UVM
• Writing detailed test plans that cover functional scenarios, corner cases, and protocol compliance for memory controller and interface IP designs
• Developing reusable verification IP and testbenches that can be adapted across multiple projects and IP variants
• Working directly with design and architecture teams to identify bugs, clarify specifications, and close coverage gaps before tapeout
• Running functional coverage analysis, tracking metrics, and driving coverage closure across complex multi-protocol environments
• Mentoring junior verification engineers on UVM best practices, debugging techniques, and verification strategy
• Using simulation tools like VCS or ModelSim to execute regression suites, debug failures, and validate design changes

You will need:

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with 6 to 8+ years of hands-on ASIC or SoC verification experience
• Proven track record verifying Interface IP protocols such as HBM, DDR, LPDDR, or AMBA in production-level designs
• Strong proficiency in SystemVerilog and UVM, including building testbenches, writing assertions, and developing verification IP
• Deep understanding of digital design concepts, timing, protocol compliance, and memory subsystem architecture
• Experience using simulation tools such as VCS, ModelSim, Xcelium, or equivalent in a regression and debug workflow
• Demonstrated ability to drive functional coverage closure and deliver fully verified IP on schedule
• Experience with HBM2, HBM3, DDR4, DDR5, LPDDR4, or LPDDR5 is a strong plus

The team you'll be part of is highly skilled and motivated, focused on delivering cutting-edge Interface IP solutions.

Rewards and benefits include comprehensive medical and healthcare plans, time away programs, family support, ESPP, retirement plans, and competitive salaries.