Description
We are looking for a VLSI CAD Timing Intern focused on Applied AI to lead end-to-end solution development for timing and constraint analysis workflows.
You will be part of a cross-disciplinary team building intelligent systems that learn from sign-off data, reason across flows, and assist engineers in achieving faster and more predictable closure.
Responsibilities
- Learn and support static timing analysis (STA) flows using industry tools like PrimeTime and Tempus for advanced ASIC designs.
- Help develop and automate timing, constraints, and QoR validation flows using scripting and data-driven methods.
- Assist with analyzing timing reports, constraints, and design data across corners and modes to improve closure predictability.
- Collaborate with CAD, physical design, and methodology engineers on timing sign-off strategies and best practices.
- Contribute to early AI- or analytics-assisted approaches for timing analysis, constraint checking, or flow optimization.
- Explore how physical effects influence timing and design decisions.
Requirements
- Currently pursuing a Master’s or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Coursework or academic knowledge in VLSI/ASIC design, digital circuits, or computer architecture.
- Exposure to applying agentic AI to back-end VLSI tasks.
- Familiarity with the basics of static timing analysis, constraints, or digital design flows.
- Knowledge in scripting or programming (Python preferred).
- Comfort working with data, reports, and technical problem-solving in complex systems.
Benefits
- Intern benefits
- Hourly rate: 20 USD - 71 USD